module top
(
    input                       clk,
    input   wire                rst,
//    output wire                 led0,
    output wire                 sys_clock_pulse
);


nios_cpu u0 (
    .clk_clk                   (    clk                ),
    .reset_reset_n             (    rst                ),
//    .led0_export               (    led0               ),

    .sys_clock_pulse_export    (    sys_clock_pulse    ),
    .nios_wr_fpga_rd_valid     (                       ),
    .nios_wr_fpga_rd_data      (                       ),
    .nios_wr_fpga_rd_ready     (    1'b1                )

);

endmodule

